Simultaneous switching noise (SSN) is defined as a noise voltage induced onto a single victim Input/Output (I/O) pin of an electronic component due to the switching behavior of other aggressor I/O pins in the device. This noise is considered in the context of either an output I/O driver victim or an input I/O buffer victim.
It is a difficult task to verify that a system design, under the influence of SSN, meets a required noise margin. Existing simulation techniques can be used to predict the magnitude of a noise event caused by a given set of aggressor signals on a victim pin, but as the complexity and size of Integrated Circuits (IC) grow, so does the amount of time required to perform SSN analysis on a circuit design, which can be in the order of hours or days. In practice, this translates as a limit to the number of possible IO layouts that a circuit designer can test using SSN techniques because the designer needs to make changes to the circuit design, run the Computer Aided Design (CAD) tool again, and then perform the SSN analysis on the new design.
Current design tools tend to clump pins together as other performance metrics tend to improve in this layout. This is done at the expense of increasing SSN, which tends to increase as pins are clumped together.
It is in this context that embodiments of the invention arise.